里面是VHDL的一些例子，大家可以看一下，蛮不错的，对大家提高VHDL水平很好的....

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information

verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)

LCD SpartaN3E fpga vi

说明：  quartus的破解软件，里面有说明文档(Quartus crack software, which contains documentation.)

cic_dec_8_three CIC 文件的ＶＨＤＬ-cic_dec_8_threeCIC documents VHDL

fpga控制da产生幅值频率可调的正弦波程序(the fpga Control da produce the amplitude adjustable frequency sine wave program)

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

本白皮书探讨了在PCI Express的因素 技术可能会影响性能。它还 提供指导如何估算 的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)

crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码，主要涉及视频开发方向。(All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.)