4X4键盘密码比较模块，可以查看密码6

RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)

原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)

ps2 vga interface in vhdl code

自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!

vga显示彩色图像ip，alter开发板-vga display color image,vhdl,quartus

AES128 encription vhdl code

Altera DE1平台的数字密码锁设计，可以驱动VGA显示(Altera DE1 platform digital password lock design, can drive VGA display)

说明：  AXI verilog designs with testbench: AXI-lite, AXI, AXI-stream

四位全家器的VHDL语言模块，已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through

《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5