4X4键盘密码比较模块，可以查看密码6

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

应用vhdl语言进行加法器的设计，比较器的设计，随着vhdl语言的应用越来越广泛，其重要性也更加明确。希望对大家有所帮助。-application vhdl language adder design, compared with the design, With vhdl language widely used, the importance of which was more explicit. We want to help.

用FPGA实现SDRAM的操作，具体操作见内部说明文件-FPGA SDRAM with the operation of the specific see internal note

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

一个完整的基于FPGA的IIR低通滤波器的设计方案，是一个研究生论文(master and doctor dissertation)

verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

给出了脉冲多普勒雷达相参积累的vhdl程序，可作为参考。主要的是设计思想，看之前得掌握相参积累的原理

通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)

9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)