crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,

QAM调制，解调matlab代码，包含BPSK，QPSK,16QAM,64QAM,256QAM,1024QAM,4096QAM。其中调制方式。代码通过验证。(QAM modulator,demodulator)

VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

Fun little FPGA that plays a portion of Habanera

总结设计中的重点及注意的地方，常出现错误的地方等。-Summarize the design of the focus and attention of local, often the wrong place and so on.

VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)

说明：  ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface