verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过...

VHDL与源代码包-and VHDL source code

说明：  isa MEMORY PLAN eu biu asm

通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)

说明：  FPGA控制外边led，并实现跑马灯等多种效果，用户可以自行控制(FPGA control outside led)

VHDL examples for counter design, use QuickLogic eclips

实现两路数字信号的鉴相功能，最后通过静态LED显示出来，该程序通过硬件的测试-Realize two-way digital signal phase function, and finally through a static LED display, the program through the hardware test

二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider

这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序，FPGA是Xilinx的virtecx-5，这是我在做毕业设计的时候自己编写的，希望能对你有帮助！(This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate design time I have written, I hope you can help!)