异步FIFO

利用Verilog编写的 小程序源码及测试,包括流水灯，交通灯 ，等小程序。

说明：  基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)

fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

verilog源代码，实现两种方法的模3运算。(verilog source code，to implement the calculation of mod-3 by two means.)

VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)

FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company:  // Engineer:  //  // Create Date:    19:40:20 01/09/2019  // Design Name:  // Module Name:    fulladder  // Project Name:  // Target Devices:  // Tool versions:  // Description:  // // Dependencies:  // // Revision:  // Revision 0.01 - File Created // Additional Comments:  // ////////////////////////////////////////////////////////////////////////////////// module fulladder(     input a, b, cin,     output s, cout     ); assign s=a^b^cin; assign cout= a&b| b&cin | cin&a; endmodule

VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)

用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)

有三个基于FPGA驱动高速AD/DA的程序、硬件电路图、使用向导手册、连接方法，支持ADDA_AX301，ADDA_AX415，ADDA_DB2C8，可以下载到 FPGA 黑金开发板、FPGA 黑金开发板学生版结合相关模块进行使用，