吠陀乘数

A VANET research program

注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)

数字电路与逻辑设计实验编程，包含多功能电子钟程序，实用，简易(Digital circuits and logic design experiments programming, including multi-function electronic clock procedures, practical, simple)

连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)

在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下 变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所 采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字 下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了 数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)

OFDM中的IFFF模块实现，基于verilog实现，通过验证(OFDM module in IFFF)

在FPGA中编写FPGA芯片与DSP28335进行通信的程序(FPGA chip and DSP28335 written in FPGA communication program)

VHDL Vendingmachine source

以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)

emmc协议的实现代码，包含了SD协议，usb实现协议(The implementation code of EMMC protocol)