32位元浮点数加法器,用于以VHDL编写的32位元CPU

2004 SNUG of systemverilog

说明：  串口通信vivado实现，带有仿真文件，可实现数据收发(the uart program based on vivado)

关于MPEG压缩的程序，里面有较多的源代码和完整的说明是用MICROBLAZE完成的。(On the MPEG compression process, there are more source code and complete description is completed with MicroBlaze.)

这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)

bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

两篇中文论文，详细叙述了Farrow滤波器的设计方式和理论基础，非常实用！(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)

uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

该程序是在d，t，jk触发器上用vhdl语言编写的

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)

说明：  简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)