用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过

根据按键控制状态机状态转换，内含仿真波形文件

lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)

这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10

用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock

Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)

Multi-Digital Down Converter design.

说明：  I2C完整代码，可综合，可仿真，已经过验证(I2C code can been syn and simulation ,veritify)

floating point divider

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)