用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过

说明：  DOCUMENT ON DISTRIBUTED ARITHMATIC

由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and all the procedures.

这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem )

URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)

SDRAM的驱动程序，主要是对SDRAM各类状态进行驱动，有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)

说明：  Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)

串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar

VHDL实现国家SM4加密算法（ECB）模式 (VHDL to achieve national SM4 encryption algorithm (ECB) mode)

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.