用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过

VHDL数字系统设计和工程实践1，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.

tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)

I2C端口的FPGA实现，网上较多，但发现不少有问题，这个是在网上代码的基础上修改过，验证可行。-I2C port FPGA, online more, but found that many problems This is a code on the Internet on the basis of the revised test feasible.

build synthesizer on a de2 dev fpga board

quartus 中，自己写的tcl，分配io的例子。-Quartus in their own writing tcl, distribution io example.

VHDL语言实现VGA的显示彩条横条九宫格的功能。(VGA display color of the VHDL language bar Jiugongge function.)

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

说明：  Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

maxplus2为开发环境 vhdl编写的 键盘 程序-maxplus2 VHDL development environment for the preparation of the keyboard procedures