用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过

对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656

VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)

FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

说明：  Verilog开发的，MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)

verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )

非常优秀的国外VHDL设计教程，可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation

ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

一个简单的23计数器，用VHDL实现，可供初学者学习。(A simple 23 counters, with the VHDL implementation, available for beginners.)

wavelet transform of a signal,it is important and useful code to trans form frequency to time domain

I2C EEPROM 存取源碼, 通用ATMEL(I2C EEPROM read/write)