VHDL version of the C8051 core (C8051). Evatronix company s IP core

连乘,乘法可以用简单的for循环，我这里用的是移位寄存器来做，而且是用来两个移位寄存器(this is a tool that function is multiplay,it use a special way to do multiplay .it will teach you the how to use labview )

alu 模块，算术逻辑单元，实现简单的控制模块，有最基本的几条指令-alu instruction

VHDL实现快速傅里叶变换，内附带资料以及源代码。(VHDL fast Fourier transform, within the supplied data and source code.)

AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

EP2C35A实验箱基于NIOSII的串行AD_DA编程(EP2C35A experimental box based NIOSII the serial AD_DA programming)

关于ALTERA DE2板上的文档资料，包括应用实例，用户文档和板上常用器件的技术文档(datasheets of ALTERA DE2)

ODBC编程实例，使用ODBC对基于开关量数据采集卡的通信接口设计与实现。(ODBC programming examples, using ODBC for data acquisition card based digital communications interface design and implementation.)

嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl

GF_2_m_域乘法器的快速设计及FPGA实现，对于rs编翼码的理解和设计有帮助-Domain multiplier GF_2_m_ rapid design and FPGA realization for rs wing made the understanding of code and design has helped