VHDL version of the C8051 core (C8051). Evatronix company s IP core

NIOSII I2C接口模块及驱动程序，并含有测试程序。对想开发NIOS的工程师很有帮助-NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful

this is a verilog code of true random number generator using butterfly puf

实现fpga上交通灯的设计，可以在开发板上实现红绿灯(Design of traffic lights on FPGA)

here is realized simple FIFO stack in vhdl. very simple example, but very helpful.

说明：  这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

基于FPGA与LM4550B的AC97软声卡VHDL语言驱动，版本2.0-FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0

COUNTER 用于xilinx硬件，里面已建工程，修改ucf即可。设计由3部分组成，计数器，100M分配时钟，顶层模块，其中顶层模块包括计数器和分频器。

基于Verilog的数码管模拟扫描程序，分为两种显示方式，一种是数码管逐个显示，另一个是所有数码管一起显示。-Verilog-based digital control analog scanning procedures, two types of display, a digital control-by-show, and the other is with all digital tube display.

可综合的Verilog语法（剑桥大学，影印）.(A comprehensive Verilog Grammar (University of Cambridge, photocopy).)