VHDL version of the C8051 core (C8051). Evatronix company s IP core

采用VHDL编写的七段数码管显示程序-prepared using VHDL paragraph 107 of the procedures Digital Display

FPGA跑马灯程序,基于CPLD1270开发板的运用程序-Marquee program FPGA-based development board CPLD1270 the use of procedures

用VHDL语言编程完成数码管0-255数字的显示-VHDL language programming with the 0-255 number to complete the display of the digital control

这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240

6位密码锁，密码锁控制器是硬件与软件的结合。根据设计要求，决定以FPGA芯片和VHDL语言设计此电子密码锁(6 locks, the lock controller is a combination of hardware and software. According to design requirements, the decision to the FPGA chip and VHDL design electronic locks)

DAC0832的Verilog代码，适用于与ADC0809同时学习，效果明显！(DAC0832 Verilog code, applicable at the same time with ADC0809 learning, the effect is obvious!)

数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems.

this files in Quartus2 are fulladder

说明：  PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)

用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)