16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)

伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)

用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--

在BASYS3上实现跑马灯的功能。第一LED交替闪烁；第二LED由左至右逐个变亮，再逐个变暗；第三LED由右至左逐个变亮，再逐个变暗；第四LED由两边逐个变亮，再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)

uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

floating point divider

vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)

带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!

一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter

使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation