16位CUPIP核,完全运行的好的东西,可以直接拿来用的!

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

利用FPGA，产生三相SPWM波，与后继硬件电路配合，形成三相电源。高效，实用。(Using FPGA, produce three-phase SPWM wave, with subsequent hardware circuit with the formation of three-phase power. Efficient and practical.)

电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed

Quartus? II 相关的语言 详细介绍了VHDL verilog软件开发过程(Quartus ? II related language detailed introduces the verilog VHDL software development process )

QFSK的调制与解调，用C写的主程序，汇编写的调制与解调的子程序(QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram)

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

it is a new describng system for it field

fpga实现ddr数据收发测试，完整的工程，下载解压后，即可正确运行，已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)

Bucknell Verilog Manual