SOPC软件编程基础，用实例讲解，非常适合初学者。

利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)

从FIFO到到RS232的实现，用于接收和缓存数据(TripAdvisor RS232 FIFO implementation for receiving data and cache)

说明：  Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)

ＦＰＧＡ与ＳＤＲＡＭ　的　ＶＨＤＬ　接口设计(ｔｈｅ　interface of FPGA and SDRAM)

这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

说明：  Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes. The representation step specifies the mapping the phenotypes onto a set of genotypes. Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space. Chromosome, and individual can be used for points in the genotye space. Elements of a chromosome are called genes. A value of a gene is called an allele. Variation Operators The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.

高精度小数除法器设计与实现。 在FPGA开发板上实现小数除法器，输入输出信号N_in [15:0], D_in[15:0]，N_in[15:0]小于D_in，即被除数小于除数，输出商Q_out[15:0]中Q[15]一定为0，Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)

HDMI协议的Verilog实现，通过对RGB三个通道分别进行TMDS编码完成，纯原创代码(Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code)

用FPGA verilog hdl实现千兆以太网MAC。-Using FPGA verilog hdl realize Gigabit Ethernet MAC.