Input from the MIC for some audio and then AOUT interface from broadcast in the...

VHDL与源代码包-and VHDL source code

一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read

基于FPGA的希尔伯特变化的verilog代码(Hilbert change verilog code)

isa总线接口，可以实现与isa总线　的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)

HLD开发语言ADHL介绍。ADHL是ALTERA公司开发的硬件描述语言，也是一种较为流行的开发工具。是介绍AHDL的入门培训资料。-HLD development language ADHL introduction. ADHL is ALTERA developed hardware description language, but also a more popular development tools. AHDL is the introduction of induction training information.

this program does something im not sure what but all i want is to get into the damn site thank you

通过FPGA实现整数阶混沌系统，通过定点数的方式，全并行。(The realization of integer order chaotic systems through FPGA)

说明：  用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)

SDRAM驱动器，自己项目利用的，已经经过实际验证(sdram controller)

Join repetitive control, Very convenient to use, Iterative self-organizing data analysis.