Input from the MIC for some audio and then AOUT interface from broadcast in the...

运用vhdl程序设计语言进行ppm设计，ppm 设计在vhdl语言中非常常用，运用已经越来越广泛。-use vhdl program design language ppm design, vhdl ppm design in a very common language, has become increasingly widespread use.

这是一个nios工程，控制TFT液晶屏的程序。FPGA平台用Verilog HDL语言编写的，MCU软核程序有C语言编写。通过这一个完成的工程，你就会明白SOPC的一些实现方法。(This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written in C language. Through this a complete project, you will understand some of the SOPC methods of realization. )

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new design

数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能(Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when)

这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down

here is a VHDL example

16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL

this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.

自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)

用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--