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简单的Verilog程序，针对音频实验板的AD到DA调通试验，下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform. Please configure it according to the test environment before download and implement the program to FPGA)

VHDL语言，实现穿行数据接收的功能，将异步串口的数据转换为八位数据存储。

verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control

说明：  设计一简易数字频率计，其基本要求是： 1)测量频率范围0～999999Hz； 2)最大读数999999HZ,闸门信号的采样时间为1s；. 3)被测信号可以是正弦波、三角波和方波； 4)显示方式为6位十进制数显示； 5）具有超过量程报警功能。 5)输入信号最大幅值可扩展。 6）测量误差小于+-0.1%。 7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are: 1) The measuring frequency range is 0-999999 Hz. 2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s. 3) The measured signal can be sine wave, triangle wave and square wave. 4) The display mode is 6-bit decimal number display. 5) It has alarm function beyond range. 5) The maximum amplitude of input signal can be expanded. 6) The measurement error is less than +0.1%. 7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)

? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 ? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 ? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 ? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 ? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

48阶FIR设计，采用VHDL语言描述，门级映射……(48-oders FIR design with VHDL language and gate level)

Simple relay trigger

verilog 我自己写得按单脉冲发生器，通过了综合和仿真，和频率可变的正弦波发生器，-verilog I write by a single pulse generator, through the synthesis and simulation, and variable frequency sine wave generator,

《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)

用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program