This document is formatted UltraEdit document describes some of the original Ult...

用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate

基于alteraCPLD芯片的VHDL点阵滚动显示源代码-VHDL-based alteraCPLD chip dot matrix rolling display the source code

硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.

这是自适应滤波器，使用verilog代码来编写的，已通过了仿真，效果很好。希望能给大家好好分享！(This adaptive filter verilog code to write, through a simulation, with good results. I hope to give a good share!)

all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

QAM调制模块，可用于Quartus仿真与fpga硬件实现。(QAM Modulation Mode, can be used for Quartus simulation and FPGA.)

adpcm .c程序代码，完整,通过编译仿真(ADPCM c program code, complete compiled simulation)

ULTRACTR的源码，xps工程实现，基于PPC平台-ULTRACTR source code, xps engineering, based on the PPC platform