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ethernet_tri_mode_rtl.tar
以太网控制器verilog,含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)
- 2007-12-19 23:51:08下载
- 积分:1
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PID
用Verilog HDL编写的PID程序代码,成功调试,运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)
- 2012-03-09 11:18:17下载
- 积分:1
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c8
说明: QPSK 调制 与 解调的源代码 可综合 出波形(QPSK modulation and demodulation of the source code)
- 2011-03-04 00:17:17下载
- 积分:1
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01_rtc_ds1302
说明: 实现基于黑金开发板的实时时钟功能,显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)
- 2021-01-11 14:40:12下载
- 积分:1
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std_ovl_v2p7_Feb2013
目前最新的OVL库,里面是标准的ASSERTION模块,支持VHDL刚Verilog,最近在做AXI协议验证的时候用到,分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)
- 2021-04-28 21:38:43下载
- 积分:1
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基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出...
基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output
- 2023-03-31 21:30:04下载
- 积分:1
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banjian
完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)
- 2015-06-26 21:17:49下载
- 积分:1
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dct
基于FPGA的图像压缩算法程序,自己写的,可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)
- 2011-10-23 00:54:17下载
- 积分:1
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04432909
基于FPGA实现的神经网络算法ANN。针对手势识别,不错的参考文章。(Hand Postures Recognition System Using Artificial Neural Networks
Implemented in FPGA)
- 2015-06-25 06:34:19下载
- 积分:1
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parallel adder
- 2022-05-21 10:17:30下载
- 积分:1