华为如何规范软件代码写作，

卷积码（2,1,4）编解码的FPGA实现(Convolution code (2,1,4) decoding the FPGA implementation)

Verilog HDL 写的SVPWM 算法的实现，使用的是altera 风暴系列的FPGA，占用资源1w+逻辑宏单元(Verilog HDL ，SVPWM)

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

实现拟想要的音乐，基于at89s51单片机的电子琴设计！(To achieve the desired music to be based at89s51 keyboard microcontroller design!)

Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.

verilog设计的32位IO口扫描后通过串口发送到计算机(Verilog design of 32 bit IO export after scanning through the serial port to the computer)

图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)

基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)

FPGA板上的锁存器PLL控制代码（verilog代码）(FPGA board latch the PLL control code (Verilog code))

Description of a sistolic arhictecture for a FFT implementation in FPGA.