华为如何规范软件代码写作，

最新热血江湖外挂，需要的可以下载，游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface

verilog alu 8bit for engineers

说明：  基于FPGA的VGA驱动代码VHDL 在显示屏显示一个汉字(FPGA-based VHDL code of the VGA driver that a character in the display)

用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest

FPGA读取LM75A温度数据，并在段码LED上实时显示。(The temperature data of LM75A are read by FPGA and displayed on segment code LED in real time)

ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。(some modules used in ASIC design.)

TR0114 VHDL Language Reference