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tcpip_stack_v1_2
说明: 实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输,对TCP的连接、接收、发送、断开均经过测试,功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)
- 2020-05-05 10:03:04下载
- 积分:1
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CPU
十一和通过vivado实现多周期cpu,各种作业再里面包含了(Realizing multi period CPU)
- 2020-12-29 10:19:00下载
- 积分:1
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GMSK
GMSK基带信号的调制解调基于SIMULINK的系统,计算误码率,(Modulation and Demodulation of GMSK Baseband Signal)
- 2019-04-18 15:33:07下载
- 积分:1
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Verilog HDL实现的I2C Slave模拟
Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
- 2022-11-26 13:05:03下载
- 积分:1
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fpgaspi
LabVIEW FPGA SPI implementation
- 2013-04-30 00:03:18下载
- 积分:1
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PN_GEN
说明: 一个PN序列发生器,大M序列,供参考学习,(A PN sequence generator, the M series, for reference study,)
- 2008-10-20 13:46:45下载
- 积分:1
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使用LPM_ROM的实际的例子
使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM
- 2022-10-03 13:00:03下载
- 积分:1
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I2C_ise9migration
说明: IIC 的Verilog实现,工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)
- 2010-04-02 09:26:54下载
- 积分:1
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uart766
---实现的部分VHDL 程序如下。
--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))
- 2007-06-02 12:44:31下载
- 积分:1
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ADC0832TLC5615
开关电源中用单片机产生可调电压控制PWM波程序,ADC0832读取输出电压(Single-chip switching power supply using adjustable voltage control PWM wave generation process, ADC0832 read the output voltage)
- 2011-09-16 23:37:27下载
- 积分:1