登录
首页 » VHDL » VHDL language used to achieve a display hours, minutes and seconds of the clock:...

VHDL language used to achieve a display hours, minutes and seconds of the clock:...

于 2022-04-27 发布 文件大小:374.21 kB
0 162
下载积分: 2 下载次数: 1

代码说明:

用VHDL语言实现一个能显示时、分、秒的时钟:可分别进行时和分的手动校正;12小时、24小时计时制可选,12小时制时有上下午指示;当计时到预定时间(此时间可手动设置)时,扬声器发出闹铃信号,闹铃时间为10秒,可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • This application note explains the process of eveloping and debugging a hardware...
    This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.-This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.
    2022-01-23 11:16:04下载
    积分:1
  • Nexys-4-DDR-XADC
    Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)
    2018-12-07 15:33:22下载
    积分:1
  • FFTbased-on-FPGA
    基于FPGA的快速傅里叶变换。使用ISE软件以及MATLAB验证。(FFT based on FPGA)
    2014-09-25 12:51:52下载
    积分:1
  • ModelsimPDFWordPPT
    个人搜集的各类Modelsim教程全集视频PDFWordPPT等.rar(Personal collection of all kinds of Modelsim tutorial video PDFWordPPT Complete Works, etc.. Rar)
    2009-09-20 11:37:19下载
    积分:1
  • 基于SPWM自治FPGA
    基于FPGA的自治型SPWM波形发生器的设计!正弦脉宽调制(SPWM)技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用,如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈!-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!
    2023-03-04 10:10:03下载
    积分:1
  • seven-voting
    用verilog 语言实现七人投票表决器(verilog seven voting)
    2020-09-24 10:57:48下载
    积分:1
  • SDRAM控制器设计代码
    SDRAM控制器设计代码,我们写的SDRAM控制器是肯定包括初始化、读操作、写操作及自动刷新这些操作的,既然这样,我们就可以给每一个操作写上一个模块独立开来,这样也便于我们每个模块的调试,显然这种思路是正确的。那怎么让我们的各个模块工作起来呢,虽然都是独立的模块,但很显然这几个模块之间又是相互关联的。就拿上面刚才说的那个情况来讲,如果SDRAM需要刷新了,而SDRAM却正在执行写操作,那我们刷新模块与写模块之间怎么进行控制呢?这个问题解决了,读模块与刷新模块之间的这个问题也可以很轻松的解决。
    2022-03-21 02:39:52下载
    积分:1
  • zidongmen1
    控制步进电机转动,正反转,旋转角度完美掌握。很好用,亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
    2018-12-25 16:41:07下载
    积分:1
  • 100powertips
    these are the source codes for the book " 100 power tips for FPGA designers"
    2012-08-20 14:59:29下载
    积分:1
  • PWM
    自己编写的verilog语言 PWM实现的一种方法希望有用(verilog PWM)
    2015-04-05 18:23:37下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载