基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细...

利用EGO1数模混合口袋实验平台上的蓝牙模块与板卡进行无线通信。使用支持蓝牙 4.0 的手机与板卡上的蓝牙模块建立连接，并且通过手机 APP 发送命令，控制 FPGA 板卡上的硬件外设。(The Bluetooth module on the EGO1 digital-analog mixed pocket experimental platform is used to communicate with the board. The Bluetooth 4.0-enabled mobile phone is used to establish a connection with the Bluetooth module on the board, and commands are sent through the mobile phone APP to control the hardware peripherals on the FPGA board.)

说明：  关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试(on an eight processors, and source code, VHDL design, the test)

Altium Reference design for LMH0340 test bed and design

若农场路无车辆，则在高速路保持绿灯。在探测农场路有车辆，高速路上的交通灯应由绿到黄，再到红，并允许农场路方向灯变绿，绿灯亮一段时间，由绿变黄再到红。(If there is no vehicle on the farm road, keep the green light on the highway. There are vehicles on the farm road, the traffic lights on the high speed road should be green to yellow, and then red, and allow the farm road lights to turn green, the green light for a period of time, from green to yellow, then to red.)

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .

任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.

双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT STATIC RAM)

AD9268的配置Verilog实现，程序用于实现4通道的AD9268的配置(The 4 channel AD9268 configuration)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

About 1588 PTP protocol xillinx FPGA running code and Software application, and to introduce documents, want to help everyone