用VHDL语言实现CPLD（EPM240T100C5组成）串口接收程序

四人抢答器，包括主持人清楚按键，抢答后屏蔽其他三人的继续抢答，同时答题时间开始，答题时间三档可调。时间到后蜂鸣器发声，指示灯亮起。

DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器(DDS_AD9854_for FPGA, verilog source code, signal generator.)

Lift Controller in vhdl using process statement and state disgram

Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

verilog vga 图像处理(verilog vga)

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件-Such as precision digital frequency of a project- including VHDL source code and compile the relevant documents after

无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)

verilog code for apb to ahb convert