用VHDL语言实现CPLD（EPM240T100C5组成）串口接收程序

VGA interface using Spartan3E board from DIGILENT.Labview .vi

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理(A simple realization of a vending machine with verilog state machine design, there are design principles introduced word)

利用matlab、xilinx13.4和ipcorefir编译器5.0进行了低通滤波器的设计。所附的代码将帮助您制作所需频率的低通滤波器。fir编译器有许多不同类型的规范。您可以根据您的要求提供所有规格。这里采样频率为700hz，通带频率为35hz，阻带频率为40hz。在分配完所有的值之后，您可以在matlab中生成滤波器的系数。matlab将生成.coe文件，您可以在FIR编译器中浏览该文件。它将生成一个文件，您可以在ADCU DAC代码中实例化该文件，并获得所需的输出。

本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.

modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

LED based video wall tech spec

说明：  银行排队系统的VHDL程序实现，可以实现排队顾客自动取号，查看前面排队人数，银行服务柜台号等。(Bank queuing system VHDL program can be achieved automatically check its customers lined up to view the queue in front of the number of its banking services, such as counters.)