FPGA实现12路pwm

135个经典VerilogHDL源码和说明文档，入门的好资料-135 Classic VerilogHDL source and documentation, a good data entry

Documentation Of Digital Electronic Systems With VHDL from US DOD.

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

AHB to Wishbone memory interface VHDL source code

说明：  通过按键输入学号，并循环显示： 电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle: Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)

HDL编程风格，很有用,希望对大家有所帮助。-HDL programming style, very useful, we want to help.

VHDL code comparator

串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar

说明：  半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

基于FPGA的键盘PS第二类编码方式的verilog解码程序。基于FPGA的键盘PS第二类编码方式的verilog解码程序。(FPGA keyboard PS encoding the verilog decoding procedures. FPGA keyboard PS encoding the verilog decoding procedures.)