FPGA实现12路pwm

Decoder using Miller method for UHF reader

verilog例子很丰富，几个经典的,希望对初学者有所帮助-verilog examples of very rich, a few classic, and want to be helpful for beginners

基于VHDL语言描述的一个分频器，根据端口值，可作为四分频，八分频等分频器使用。-based on VHDL description of a divider, according to port value, as a quarter of frequency, Frequency Divider interval such use.

自己编写的只读存储器ROM16*8的试试很好用的-ROM 16*8

RGB vga driver for manipulating the colours of a given image buffer. The code has beeen written in vhdl

实现QPSK系统的调制解调仿真，基带成形滤波器采用升余弦滚降滤波器，将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)

说明：  misp，五级流水源码，实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)

matlab 编的瑞利信道仿真源码，对研究信道很有用(hgajdjkjhakhdkhakjlkjlka)

Verilog经典教程，很好的学习Verilog的书籍，对学习硬件编程很有帮助。(Verilog classic handbook, good learning Verilog books, to learn hardware programming helpful.)

AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.