FPGA实现12路pwm

自适应滤波，对输入信号进行选择性的加权处理，使输出达到最优化，并且能够跟踪和适应系统和环境的动态变化(Least mean square，of the input signal processing, selective weighted output, and optimize can track and adapt to the dynamic changes of the system and environment)

这是一个版本的mp3播放器的迷你尺寸，你可以把它与AVR编程非常easy.it在这个项目这么简单，你使用的fat通过MMC的SPI总线，该总线使主从位置发送数据，然后用此主从，你可以从VS1003发送数据到你的ATmega8然后有一个非常简单的项目。

uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

主要给出准循环的LDPC码编码实现方法，译码方法选择，并给出了帧同步的解决方法(Give the main quasi-cyclic LDPC codes achieve coding method, decoding method of selection, and give the frame synchronization solution)

基于NIOS2的VGA接口IP核，具有很好的借鉴性和参考性(NIOS VGA IP)

xilinx Spartan 6 PCIE仿真教程，PIO方式，带有TLP包分析。(XILINX PCIE tutorial device spartan6 PCIE core version V2.4)

本文提供了一种CMOS控制器，使Nios-II可以利用CMOS控制器控制CMOS，并允许在CMOS图像上传送SDRAM。在DE2-70平台上运行

如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。 (As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)

关于数字电压表的vhdl实现，有仿真程序，可以下载到板子中。(Vhdl digital voltage meter on the implementation of a simulation program can be downloaded to the board.)

1602是目前最常用的显示器件，本例是通过verilog 代码实现1602的显示(1602 display)