FPGA实现12路pwm

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

its a Fifo BASED design i also Interface DAC2904

costas载波恢复算法 锁相环路，注释很清楚(costas carrier recovery algorithm PLL)

Convolutional neural network code for fpga

here is gangadhar call by mailing me

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

practical_lift_controller 实用电梯控制器 实用电梯控制系统block symbol file 实用电梯控制器的Verilog HDL程设计-practical utility practical_lift_controller elevator controller elevator control system block symbol file utility elevator controller Verilog HDL-way design

使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存(Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache)

基于FPGA微分程序代码及其电路驱动程序(Based on FPGA differential program )

32bit floating point addition