速率发生器

本文件时VHDL的各种编写规范，有助于开发者在平时养成好的编码习惯(This document, the various write VHDL specification, helps developers to develop good coding habits in peacetime)

六十进制计数器，VHDL编写的计数器，本科电子的可能有些实验可以用到(counter Possible experiments of undergraduate electronics can be used)

Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现(Verilog，Sobel Operator)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

FPGA实现1553B编解码器功能 Verilog语言(FPGA implementation of 1553B codec function, Verilog language)

Verilog代码为Sigma-Delta ADC的实现。Verilog是包含testbench。NDIFF V。V的冬天。readmem V。V梳状滤波器。combfilter_tb V。combfilter_wrap.vhd

dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)

双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT STATIC RAM)

完整的GMSK调制及维特比译码，程序中包括了高斯滤波器的设计，调制相位的计算，并采用了维特比译码算法解调出原始码元，最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)

好用的SDRAM控制器，经过FPGA平台验证过。(It is a SDRAM controller with verilog code. It is a good code, and confirmed.)