速率发生器

用verilog hdl编写的248分频器,有助于对verilog编程语言的了解，可直接用于FPGA编程

加法器，输入两个整数，用电路图形式将其逻辑原理呈现出来，该加法器为8位运算，每一位都对应一张电路图，可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)

说明：  在FPGA内，实现PS2键盘数据读取功能，verilog源代码(In the FPGA, achieving PS2 keyboard data read functions, verilog source code)

这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)

半加器使用Verilog编码用于Xillinx

用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)

基于FPGA的深度学习加速器设计与实现，帮助你增加对深度学习的理解，而且作为中文，很适合国内学者。(Design and implementation of deep learning accelerator based on FPGA)

16*16点阵横向移动显示！采用QUARTUS II 9.0编译通过！(16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!)

Verilog语言的流水灯设计程序，对初学者很有用。(Water lights Verilog language design program useful for beginners.)