廉价 FPGA 实现模拟示波器方式显示

verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）(verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz))

Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.

一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。(One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.)

采用倍频及1/3、1/12倍频绘制的路面不平度频谱图（自编）(Using octave and 1/3, 1/12 octave drawn road roughness spectrum (self))

64-point FFT/IFFT processor architecture : Rrdix-SDF

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)

说明：  浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)

说明：  Xilinx ISE License集合，包含Vivado、ise的破解license，安装ISE后loading license即可完成，最全的器件库(Xilinx ise license Collection, including Vivado and ISE cracking licenses. After ISE is installed, the loading license can be completed, which is the most complete device library.)

说明：  基于altera fpga的fir IP核实现希尔伯特变换，有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)