廉价 FPGA 实现模拟示波器方式显示

我以altera公司的 FPGA，型号是DE2 系列 软件的版本是quartusii  9.0  程序实现了2,4,6,8，分频，

SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。(Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.)

绝对可用，仿照了很多代码修改而来，理解简单，只要细细阅读绝对明白，而且以后可以移植到其他程序里。顶端程序看似复杂，其实简单。module vga_module (         CLK_50M, RSTn,     VGA_HS,  VGA_VS,     VGA_BLANKn,      DAC_CLK,     VGA_R, VGA_G, VGA_B 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface

RTL_NAND_Flash_controller-master，基础入门控制器，内存管理，fpga实现。miicron所属，

利用基本全加器的逻辑表达式，写单个加法器模块。 通过模块例化，直接级联加法器，同时在输入输出端口加入寄存器。 最后可以实现不考虑进位的加法。

this program get 20 point from user and draw functions.

FFT 8 PT RDX 2 USING VERILOG