-
coverlater
本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码,能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)
- 2021-03-13 20:49:24下载
- 积分:1
-
chengxu
数字时钟,可以实现(1) 显示日期功能(年、月、日、时、分、秒以及)
(2) 可通过按键切换年、月、日及时、分、秒的显示状态
(3) 可随时调校年、月、日或时、分、秒
(4) 可每次增减一进行时间调节
(5) 可动态完整显示年份,实现真正的万年历显示
(6) 可显示温度
(Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature)
- 2012-10-15 00:25:33下载
- 积分:1
-
project_comfinal
it can add two numbers and shows the answer
- 2019-05-28 19:16:02下载
- 积分:1
-
用于FPGA的huffman算法的HDL编码
用于FPGA的huffman算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。(The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.)
- 2008-08-01 17:25:44下载
- 积分:1
-
can-lite-vhdl-master
CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分:1
-
Lab15_sw2reg
开关数据加载到寄存器并显示的设计与实现.3. 设计一个可以把4个开关的内容存储到一个4位寄存器的电路,并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse, 用btn[0]作为输入;8位寄存器模块,用btn[1]作为加载信号;7段显示管上的显示模块x7segbc;分频模块clkdiv,用以产生模块clock_pulse和x7segbc的clk190时钟信号。(Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.)
- 2014-03-30 09:50:48下载
- 积分:1
-
ethernet_mii_udp_1
说明: Verilog开发的,MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)
- 2020-03-20 16:19:21下载
- 积分:1
-
fifo
异步FIFO
输入: 16bit
输出:16bit
深度:256(Asynchronous FIFO
Input: 16bit
Output: 16bit
Depth: 256)
- 2017-07-10 14:02:36下载
- 积分:1
-
Verilog代码支持IO中断的CPU实现
Verilog代码,支持IO,中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)
- 2020-07-05 20:28:59下载
- 积分:1
-
s3esk_picoblaze_dac_control
This is the Spartan 3E tutorial_02.
- 2017-08-07 13:54:36下载
- 积分:1