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dds_test
说明: 直接数字式频率合成器DDS设计、Verilog。
产生的信号可以是正弦波或方波、三角波、锯齿波等,自选。
采用DDS技术,将所需生成的波形写入ROM中,按照相位累加原理合成任意波形。
此方案得到的波形稳定,精度高,产生波形频率范围大,容易产生高频。
本实验在设计的模块中,包含以下功能:
(1)通过 freq 信号输入需要的频率的值;
(2)通过 wave_sel 信号选择所需的波形;
(3)通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog.
The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional.
By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation.
The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform.
This experiment includes the following functions in the designed module:
(1) Input the required frequency value through freq signal;
(2) Choosing the required waveform by wave_sel signal;
(3) Select the multiplier of waveform amplification by amp_adj signal.)
- 2019-01-19 16:07:50下载
- 积分:1
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VHDL3
说明: 一个使用VHDL进行正弦波信号产生的历程,非常有用。(A sine wave signal generator using VHDL for the course, very useful.)
- 2010-03-27 09:18:41下载
- 积分:1
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webserver_c3
The term web server can refer to either the hardware (the computer) or the software (the computer application) that helps to deliver web content that can be accessed through the Internet.(web server)
- 2014-03-23 20:00:14下载
- 积分:1
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Avt_S6LX9_MicroBoard_UCF_110127
Avt_S6LX9_MicroBoard_UCF_110127,有关xilinx spartan6开发板的相关参考设计。(Adding Custom IP to an Embedded System, the relevant reference on xilinx design.)
- 2013-07-03 11:26:20下载
- 积分:1
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tb_time_offfset
说明: offset_cancellation code for matlab to hdl
- 2020-06-17 12:20:02下载
- 积分:1
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计算机组成原理课设
计算机组成原理课程设计代码,课程设计,计组(Computer organization principle curriculum design code, curriculum design, group calculation)
- 2018-10-31 22:26:09下载
- 积分:1
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PCI_SEND
通过PCI数据传输总线,实现PC到PCI板卡的高速数据传输,PCI总线使用9054芯片进行总线协议的转换(Realizing data transmission of PCI)
- 2017-12-11 14:34:00下载
- 积分:1
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Vhdl 语言设计的 16 根 4 点 FFT
介绍了设计和功能实现的 16 点 FFT 流水线。 架构基于利用该算法的变化规律,设计了蝴蝶操作和乘法器模块。 基数 4 算法。该体系结构采用四种蝴蝶,和管道阶段优化的处理速度和地区之间取得平衡。
- 2022-02-25 05:44:40下载
- 积分:1
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FSK_FPGA
FSK模拟信号源,利用ISE7.1或以上环境打开。(FSK signal simulator.The project can be open in ISE7.1 or upgrade version.)
- 2009-07-16 17:09:07下载
- 积分:1
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AVR IP CORE
可以直接用于工程的开发和
已经通过编译和仿真
AVR IP CORE
可以直接用于工程的开发和
已经通过编译和仿真-AVR IP CORE can be directly used for project development and has passed the compiler and simulation
- 2022-02-15 18:01:54下载
- 积分:1