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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分:1
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Verilog code for RS
Verilog code for RS-(255,239) encoder.
- 2022-02-02 19:13:13下载
- 积分:1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分:1
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256M_sdram_OK
改自特权同学verilog语言写sdram测试程序;支持256M内存(verilog sdram )
- 2013-12-23 16:15:43下载
- 积分:1
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str
these are verilg prgms
- 2012-12-05 18:12:51下载
- 积分:1
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CRC_restored
mpeg-2 crcr32计算的代码,采用verilog编写,验证通过(mpeg-2 crcr32 caculate)
- 2011-09-25 10:54:08下载
- 积分:1
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VHDL
FPGA 12864显示程序 VHDL程序!!(FPGA 12864 show program
)
- 2012-05-30 22:09:54下载
- 积分:1
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LMS算法FPGA仿真
自适应滤波器算法LMS ,的FPGA实现,采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
- 2020-06-24 01:00:02下载
- 积分:1
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To increase simulation speed, ModelSim® can apply a variety of optimizations...
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
- 2022-03-06 09:05:21下载
- 积分:1
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基于FPGA的uart控制器,波特率可选,VHDL编程,Quartusii 6.0 平台,vhdl语言编程...
基于FPGA的uart控制器,波特率可选,VHDL编程,Quartusii 6.0 平台,vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming
- 2022-12-05 20:10:10下载
- 积分:1