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TCD1304_drive
FPGA驱动TCD1304AP线阵CCD,并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)
- 2021-05-15 18:30:02下载
- 积分:1
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MIPSTOP
说明: misp顶层文件,verilog实现misp架构,并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分:1
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EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。...
EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
- 2022-10-28 17:25:03下载
- 积分:1
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XILINX平台DDR3设计教程
从零开始的Xilinx DDR3 控制程序编写教程,利用MIS IP核通过自编逻辑实现对DDR3的读写,强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)
- 2018-06-05 21:28:45下载
- 积分:1
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digital_tsmc018
180nm数字教学库,内含各种标准数字单元(180nm digital lib for education, including standard cells)
- 2020-12-14 14:49:14下载
- 积分:1
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S04_基于ZYNQ的HLS 图像算法设计基础
说明: VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)
- 2020-06-17 11:40:02下载
- 积分:1
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用verilog语言实现的霍夫曼压缩编码算法
说明: 一种用verilog语言实现的霍夫曼压缩编码算法(Huffman compression implemented by Verilog)
- 2019-11-18 18:29:45下载
- 积分:1
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地铁售票系统,基于VHDL,可实现站点设置,站点选择,选择购票数量,找零等一系列功能。...
地铁售票系统,基于VHDL,可实现站点设置,站点选择,选择购票数量,找零等一系列功能。-Metro ticketing system, based on VHDL, allows site settings, site selection, choose the number of tickets, Keep the change and a series of functions.
- 2022-02-16 02:43:18下载
- 积分:1
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S03_基于ZYNQ的DMA与VDMA的应用开发
说明: VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)
- 2020-06-17 11:40:02下载
- 积分:1
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FPGA60进制数码管显示VHDL代码
FPGA设计中的60进制计数器,通过2个七段数码管系那是出来。代码简单易懂,仿真通过,而且在FPGA开发板上加载显示成功。很有用的入门代码。
- 2022-07-12 13:55:48下载
- 积分:1