基于FPGA的自动售货机控制系统设计

ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)

A multiplier unit in VHDL

一个关于VERILOG与VHDL混合编程，混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)

流水线设计是高速电路设计中的一个常用设计手段。如果某个设计的处理流程分为若干步骤，而且整个数据处理是“单流向”的，即没有反馈或者迭代运算，前一个步骤的输出是下一个步骤的输入，则可以考虑采用流水线设计方法来提高系统的工作频率。-see up

异步FIFO的实现，很经典的三段式状态机的写法。(The realization of the asynchronous FIFO, very classic three-step writing state machine.)

说明：  介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)

Complete Successive approximation Analog to digital converter along with the source code

包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程(Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project)

通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)