串行至并行转换器

应用背景pll数字锁相环在FPGA中具有很重要的作用，在提取信号同步时钟等方面都有应用。关键技术FPGA的PLL数字锁相环的实现基于verilog语言，采用鉴相器、滤波、数控振荡器、分频器的结构进行实现。

使用CycloneIV芯片，实现对高精度ADCad9226的数据采集。内有详细代码说明，并附有调试结果(Use CycloneIV, to achieve high-precision data acquisition ADCad9226. Along with debugging results)

本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。(This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL language carry out. )

贪吃蛇程序，用verilog实现，可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)

IC的设计可以分为两个部分，分别为：前端设计（也称逻辑设计）和后端设计（也称物理设计），这两个部分并没有统一严格的界限，凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design related to process can be called back-end design.)

一个关于降低现代通信系统中高峰均比信号的matlab算法，对于研究数字预失真基于FPGA实现的有一定作用！(A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect! )

说明：  一个具备bp协议典型功能的数据传输系统（超时重传机制以及托管传输）包含五个节点(A data transmission system with typical functions of BP protocol (Overtime retransmission mechanism and managed transmission) consists of five nodes)

出租车计费，器设计一个出租车自动计费器，计费包括起步价、行车里程计费、停止和暂停不计费三部分。现场模拟汽车的启动、停止、暂停和换挡状态。分别用四位数码管显示金额和里程，各有两位小数，行程 3公里内，起步费为6元，超过3公里，以每公里1.3元计费(Car repair billing device)

超級好用 25M~100HZ的除頻器 寫了好久 超級實用 歡迎下載(Super easy to 25M ~ 100HZ of divider wrote a long time super practical welcome to download)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)