DDR_SDRAM控制器verilog代码

AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)

Commponent for drivering EEPROM memory AT25320 from Avalon bus.

FPGA实验_HDB3编码器设计(包含5个模块)(FPGA design experiments _HDB3 encoder (including 5 modules))

这是 ；一种缓存设计的Verilog代码，使用先进先出算法。大约2000行代码，该程序包含缓存替换算法的实现。图像规则的选择，以及所有的模拟。这个设计有很多模块。此模块包含替换执行和测试平台

用verilog  语言写的一个fir低通滤波器的程序，原始数据通过matlab来输入，输出给matlab来显示结果

Crossroad traffic lights with visualization in tcl/tk and verilog code

这是DDR3 SDRAM的控制器内核。 默认配置支持一个64位UDIMM或SO-DIMM 支持1GB，2GB，4GB和8GB的DIMM大小 以最低DDR3传输速率600 MT / s工作 针对Xilinx Spartan 6 FPGA系列进行了优化 在不到1300行的Verilog中实现 支持BC4（Burst chop 4）读写命令和刷新命令 XC6SLX25和XC6SLX75 FPGA在-2和-3速度等级下验证了可靠的操作

基于FPGA，利用vhdl语言结合matlab工具实现dds,已经仿真(Based on FPGA, VHDL language with matlab tools to achieve DDS, has simulation)

说明：  利用正点院子开拓者fpga实现DDS功能，实现三角波、正弦波、方波的发生。(Implementation of DDS with FPGA)

ATM的功能工作.atmatmamtmtmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt