FPGA

说明：  介绍USB PHY接口中的UTMI接口， 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)

Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)

无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)

WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)

摘要：本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计，用CPLD 作为交通灯控制器的主控芯片，采用VHDL 语言编写控制程序，利用CPLD的可重复编程和在动态系统重构的特性，大大地提高了数字系统设计的灵活性和通用性。 关键词：CPLD；VHDL；交通灯控制器 中图分类号：TP39 Abstract ：This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by-Abstract: This paper introduces the CPLD chip to the traffic lights at the crossroads of design, traffic lights with CPLD as the master controller chip, the use of VHDL language control procedures, the use of CPLD re-programming and dynamic system reconfiguration in the features greatly enhance the digital system design flexibility and versatility. Keywords: CPLD VHDL traffic lights controller CLC number: TP39 Abstract: This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by

VHDL 与数字电路设计程序参考书所有程序 1-VHDL and digital circuit design process all the procedures a reference book

用VHDL编写的JK触发器  用VHDL编写的JK触发器 用VHDL编写的JK触发器

存储器DDR3在Xlinix平台上的设计教程和综合应用(Design course and comprehensive application of memory DDR3 on Xlinix platform)

采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz(Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 799.617Hz)

HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)