一个简易的数字频率计，可以对一个输入的信号频率进行测量并显示输出，适合VHDL的初学者...

Construction and Experimental Evaluations of User-Centered Power

VHDL examples for 16x16 times, if need detail pls let me know

E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)

基于altera系列芯片lvds接口的fpga设计 verilog源码-Series altera-based chip interface lvds source fpga design verilog

使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

文件名：lcd1602lib.h 内　容：1602液晶的控制端口、数据端口和相关操作(The file name: lcd1602lib. H * inside let: 1602 LCD control port, data port and related operations )

用硬件VHDL语言实现的串口通信的试验代码，可用来代替单片机的工作对串口进行测试。-VHDL language used hardware realize the serial communication of test code that can be used to replace the work of single-chip serial port for testing.

用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)

8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading

非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us