ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

关于usb调试相关测试 代码，用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)

用VerilogHDL写的spi 核的例子(A simple example of SPI core using Verilog HDL)

说明：  fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)

verilog xilinx IP实现FFT仿真(Verilog xilinx IP implementation FFT simulation)

2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)

this come from alter ,you can look and find it on line.

八阶巴特沃兹iir数字滤波器，四个二阶节，verilog代码实现，多路分时复用(batterworth，iir，8order，four second order section)

FPGA SDI 输入，HDMI输出例程(FPGA SDI_IN,HDMI_OUT)