dlatch触发器或锁存器的实现

说明：  自己写的CRC的Verilog代码，在网上收集的crc相关的代码以及crc的matlab仿真代码(The CRC Verilog code written by myself, CRC related codes collected on the Internet and CRC matlab simulation code)

ATM的功能工作.atmatmamtmtmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt

本实列自己写的状态机1101序列检测，已经在modesim上面测试通过，使用两个always块，一个写组合逻辑电路，一个为时序逻辑电路。需要的可以看看

利用状态机编写一个序列检测器，可以依照思路修改需要检测的序列！

说明：  实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输，对TCP的连接、接收、发送、断开均经过测试，功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)

8位并行转穿行发送程序，波特率可自行设置，经检验有实用效果(8-bit parallel transfer walk through the sending program, the baud rate can be set up their own practical effect inspection)

接口模块，通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块，每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器，寄存器功能可自定义。模块还包含两个全局寄存器，可实现全局复位，中断等功能。该模块以应用于实际的项目中，目前运行良好(FPGA to emif)

这是一个EOS项目中的GFP成帧结构，能够容错，可以配置字节域(This is an EOS project GFP Framing structure, be able to fault-tolerant, can be configured byte domain)

这是一个基于NIOSII的俄罗斯方块游戏设计，是基于FPGA的，利用流模式DMA传输实现游戏。(This is a box based on the Russian NIOSII game design, is based on the FPGA, and the use of streaming mode DMA transfer realize the game.)

FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)