基于FPGA按键控制VGA动态图片显示

基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 (this is source code from a book)

数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)

之前看到很多人用fpga写边缘检测，都是调用了fpga的ip，这里我把这写ip都用verilog写出来，用asic实现sober边缘检测。

说明：  一本很经典的IC设计中文入门书籍，由任艳颖，王彬编著，翻印几百万册(A very classic introduction to Chinese in IC design book, compiled by Ren Yanying and Wang Bin, reprinted millions of copies)

原创verilog_16bit_risc_cpu，带相关PPT和testbench尚未进行冲突处理，代码还比较简单，方便新人学习，毕竟处理冲突后代码将会复杂很多。 继续关注我吧！ 等我做好优化和冲突处理后，还会放出来，现在已经想好思路了，就差通宵敲代码和调试了。 给我动力，我就可以翱翔蓝天！

华为FPGA设计全套资料，学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

verilog实现计时器timer，可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)

vhdl code for carry lookahead addder

基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)