基于FPGA按键控制VGA动态图片显示

RTL8369开发资料，包括手册，图纸，Layout说明等等(RTL8369 development information, including manuals, drawings, Layout Guide.)

verilog 模糊PID 通过修改MIF文件 可以完成单个参数整定(FUZZY pid by verilog HDL)

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)

OFDM完美出图，信噪比，16QAM星座图，加窗信号时域和频域波形图(Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure)

实现多周期mips  设计一个32位MIPS多周期微处理器 具有多种 算数指令： (Design a 32-bit MIPS microprocessor multi-cycle arithmetic instructions

本文分析比较了实现开方运算的牛顿一莱福森算法、逐次逼近算法、非冗余开方算法种算法,并给出了基于的开方器的实现方法(Root operation FPGA-based implementation.pdf)

This CAN Controller was tested with the Bosch VHDL Reference Model and passed all the tests. Because of the licensing issue it can not be published on the Opencores web site. The Can Controller was also implemented in real HW (12 boards were constantly talking to each other). The included test bench is not a real test bench and should be improved. However a volunteer is needed for such a job. I can provide some help but am not willing to write it by myself.

此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)

231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创！！！！(Verilog achieve 231 convolutional code, preceded by a detailed description of the document, the source, the absolute originality! ! ! !)

基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)