基于Verilog 的电子日历与电子时钟程序，可以进行调日期、星期、时间的分钟与小时，通过几种模式来显示日历与时间。...

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage

用case 语句描述的4 选1 Mux 源码程序，好用(-4 with a case statement described 1 Mux source program, easy to use)

说明：  学习vhdl硬件描述语言的一些例子的原代码(VHDL hardware description language to learn some examples of the original code)

基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)

利用c控制adc，主要是控制字写入，状态控制。-C control the use of adc, is mainly controlled write, the state of control.

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)

用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.

说明：  浮点数加法器的源代码,实现浮点数的加法功能，浮点数遵循的是IEEE745标准(floating_piont addition)

RD1006--I2C与存储器的IP 代码及说明文档，lattice提供，I2C Controller for Serial EEPROMs 源代码可用，并且包含tb文件-RD1006-- I2C and memory IP code and documentation. Lattice offer I2C Controller for Serial EEPROMs source code available, and document contains tb-