四则计算器

pci协议主模块开发实用代码， 适合初级学习者使用 很不错(pci agreement to develop practical code, very good for junior learners)

FPGA 的UDP实现，能够实现ARP、IP、UDP协议。已经通过验证。

用于检测100MHZ频率，带51单片机软核，控制外部液晶显示器以及按键等(Used to detect 100MHZ frequency, with 51 SCM soft core, control of external LCD monitors and buttons, etc.)

Verilog HDL教程 什么是Verilog HDL？ Verilog HDL 硬件描述语言(What is a Verilog HDL tutorials Verilog HDL? Verilog HDL hardware description language)

自己编写的红外解码子程序，但CPU资源占用较高，作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)

说明：  潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)

MIPS 处理器程序，出自于《CMOS VLSI Design and Systems Perspective》书中。可以实现LB、SB、RTYPE、BEQ、J指令，仿真测试可以用。

OPSK调制解调。代码思路很清晰，也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)

Decimation-In-Time Fast Fourier Transform I"ve tried to make the implementation simple and well documented. I have not tried to make it efficient. dit.v - Contains main module. buffer.v - Contains a module for a single butterfly step. generate_twiddlefactors.py - Contains function to generate a verilog file with twiddlefactors. twiddlefactors_N.v.t - Template used to generate verilog file. dut_dit.v - A wrapper around the "dit" module to allow verification with MyHDL. qa_dit.py - A MyHDL test bench for verification. Requires MyHDL, iverilog and numpy to be installed. pyfft.py - Generates output of intermediate FFT stages. Useful for debugging.

使用信号功率计算，检测信号是否到达。从而控制后续模块，以减小系统功耗。(Signal power calculation, the detection signal to reach. To control follow-up modules to reduce system power consumption.)