axi_spi_master

说明：  用FPGA实现CNN算法，实现CNN加速(Realization of CNN Algorithms with FPGA)

在FPGA平台上运行的CNN模型，可以完成相关的功能(The CNN model that runs on the FPGA platform can complete the related functions)

说明：  文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)

基于VHDL语言的波形发生器编程设计，能够实现常用波形的产生。(Waveform generator design based on VHDL programming, to achieve common waveform generated.)

说明：  有限状态机 rtl code 和 TB验证环境(Finite state machine RTL code and TB verification environment)

中芯国际130nm库文件，在DC综合练习中可以使用，并能帮帮助理解库的含义-DC　Ｖｅｒｉｏｇ，已通过测试。 (SMIC 130nm library file, you can use in the DC Comprehensive Exercises, and help to help understand the meaning of the library-DC Veriog has been tested.)

利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)

小波变换的VHDL代码，内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)

Ethernet MAC-MII interface of Transmit

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)