sobel 边缘检测

用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)

说明：  串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)

IP 核的接口（The Avalon® Streaming (Avalon-ST) interface）的使用说明，和程序(IP core interface (The Avalon Streaming (Avalon-ST) interface) instructions for use, and procedures)

VerilogHDL教程，很详细全面的Verilog教程，循序渐进，由浅入深，十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)

说明：  八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)

通信IC设计的第二章Verilog参考学习代码，方便初学者学习入门，供学习参考用The codes of Chapter1 of《Communication IC Design》(The codes of Chapter2 of《Communication IC Design》)

用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)

180nm数字教学库，内含各种标准数字单元(180nm digital lib for education, including standard cells)

应用背景DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成DDS数字频率合成关键技术阿萨德哈撒电话撒娇的好看撒电话卡收到货看上的卡上的环境阿德阿达说的按时的卡的哈可敬的按实际打开速度阿加莎的话速度快的话阿是看得见阿克苏的较好的按键大开杀戒的话爱上空间的好看撒的阿克苏加大号上大红大框架是的哈上空间的哈桑来看的见阿达