sobel 边缘检测

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

FPGA YCbCr444转YCbCr422实验 很好的参考(FPGA EP4CE40F23C6 YCbCr444 turn YCbCr422 experiment)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像基本操作,几何变换,直方图,灰度化处理等(System Generator based image processing engineering, multimedia processing FPGA implementation source code, the basic operation of the image, geometric transformations, histogram, gray processing)

I2C总线芯片AT24C02程序设计 C++编程(I2C bus AT24C02 chip program design)

HDB3码在matlab中的仿真，包括原始码、AMI码及HDB码的相关仿真图形(HDB simulink in matlab)

资源描述基于fpga的串口通信，采用verilog语言，实验开发板与pc机之间的串口通信

1、PC和寄存器组使用时钟触发。 2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。 3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。 4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked. 2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit. 3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own. 4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)

SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)

用于实现锁相光子计数技术的累加器，verilog语言(Accumulator achieve specific cases for accumulator lock detection of photon counting technique)