SDRAM Verilog仿真模型mt48lc4m32b2

说明：  design and implementation of bist using verilog

实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)

本程序是用verilog 编写的模块，用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)

CSCC标准下的RS(255,223)码的译码器设计，采用verilog语言编程实现，在软件QUARTUS II 9.0环境下仿真通过，并在CYCLONE IV系列开发板调试通过。

半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

PS2 Module for Altera DE2

半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)

自己在ISE下用VHDL写的UART，简单，易懂(in ISE using VHDL was the UART, simple, understandable)

design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.

MD5 算法在Xilinx FPGA上的实现，希望对大家有用。(MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.)