CPLD

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

很不容易找到的资料，基于VHDL的频率计设计 希望有用-Not easy to find information on the frequency meter based on the VHDL design seek to help

Spartan 3e - Active Power Meter-Spartan 3e- Active Power Meter

以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)

PCI总线仲裁参考设计，Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)

RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine

in this code very useful for designing real number concept

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)