基于FPGA的CPU核及其虚拟平台的设计与实现

本练习的目的是检查加法、减法和乘法运算电路。每个

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the

800 x 480 / inch lcd

通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)

用于实现fpag-cpu的数据通路源代码。用vhdl编写，包括内存，寄存器组，和alu（简陋的alu，仅包含加法器）三大部分通过手动微指令输入信号，可以往内存写入数据，并加载到寄存器组中，通过alu产生结果，结果保存在一个锁存器中，可以把结果写回寄存器组或者内存。本人在quartus下编写仿真通过。附件中未给出相关工程文件。

基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA )

VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue

一个用于数字解调的应用程序，主要用于数字接收机的应用方面-A demodulator for digital applications, mainly for the application of digital receiver