ROM建立平方电路

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

这是二十四进制计数器的源程序，有需要的同学可以参照一下！(This is 24 hexadecimal counter source, needy students can refer to you!)

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

用Quartus II开发的一个十进制计数器，包括仿真波形，下载文件，是完整工程。(With the Quartus II development of a decimal counter, including the simulation waveform, download files, is the complete project.)

设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the

交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现(VHDL core)

An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.

VHDL Programing

spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)