ROM建立平方电路

说明：  掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

利用Quartus 综合简单的计时器功能，欢迎大家下载、参考。谢谢大家的支持！

说明：  USB传图至fpga板缓存至DDR内，FPGA再读出图像数据，显示在TFT彩屏上；(USB to the FPGA board cache DDR, FPGA read out the image data, display on the TFT color screen;)

16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~

VHDL源码 VHDL源码 -VHDL source VHDL source VHDL source

本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读.

一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供(VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat)

利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)