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用VHDL语言实现数字钟的设计

于 2022-10-28 发布 文件大小:52.11 kB
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用VHDL语言实现数字钟的设计,要求设计实现一个具有带预置数的数字钟,具有显示年月日时分秒的功能。用6个数码管显示时分秒,set按钮产生第一个脉冲时,显示切换年月日,第2个脉冲到来时可预置年份,第3个脉冲到来时可预置月份,依次第4、5、6、7个脉冲到来时分别可预置日期、时、分、秒,第 8个脉冲到来后预置结束,正常工作,显示的是时分秒。Up为高电平时,upclk有脉冲到达时,预置位加1.否则减1。

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