用VHDL语言实现数字钟的设计

FPGA对SDRAM进行读写测试程序，亲测有效无误。(FPGA reads and writes test programs for SDRAM.)

VHDL设计的功能齐全的交通灯程序，经过仿真一切功能符合要求。-VHDL

说明：  基于FPGA的QPSK系统仿真及验证，硬件部分。(Simulation and verification of QPSK system based on FPGA)

wavelet transform of a signal,it is important and useful code to trans form frequency to time domain

说明：  千年服务端修改工具，千年db数据在线修改(Millennium server modification tool Millennium server modification tool)

使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)

FPGA——IP_RAM实验： 创建IPRAM核，单端口，10位地址线（256字节），8位数据线（每字节8byte），读写使能 input [9:0] address; input clock; input [7:0] data; input wren; //置1则写入 output [7:0] q; LNXmode：控制LEDC显示 1：mode1，从k1~k3输入data的低4位，ledb计时，从0~f，计时跳变沿读取k1~k3的值，存入RAM 8个数之后，从RAM输出数据，用leda显示，同样每秒变化一次(The experiment of FPGA-IP_RAM: Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)

说明：  实现主干道交通灯显示，以状态机程序实现，并用数码管进行红绿灯倒计时的显示，内置计数模块，交通灯控制模块，数码管显示模块，并对各模块用电路图的方式进行连接。对于学习VHDL语言有所帮助。(The main road traffic light display is realized by the state machine program, and the digital tube is used to display the traffic light countdown. The counting module, the traffic light control module and the digital tube display module are built in, and each module is connected by the circuit diagram. It is helpful for learning VHDL.)

说明：  FPGA和双端口RAM的DDS任意波形发生器的实现(FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator)

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.