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First_conv
mimo—ofdm线性卷积,实现输入的800位宽的数据同两个序列的卷积(Mimo- ofdm linear convolution
800 bits wide input data with the convolution of two sequences
)
- 2013-03-30 09:18:56下载
- 积分:1
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通信协议AHB_LITE
AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
- 2020-12-15 10:09:14下载
- 积分:1
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VGA-VHDL-Design
本文件给出了基于VHDL语言的VGA图像显示程序及其工程问件。(This document is presented based on VHDL language VGA image display program and the project asked the pieces.)
- 2010-06-19 11:35:12下载
- 积分:1
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2010_5
PI控制器的算法及源码,迅速掌握FPGA的VHDL算法实现!(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)
- 2014-07-04 15:25:59下载
- 积分:1
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AV视频信号输入后,存入SDRAM中然后在PC上面进行显示的代码。...
AV视频信号输入后,存入SDRAM中然后在PC上面进行显示的代码。-AV video signal input into the SDRAM in the PC and then display the code above.
- 2023-03-27 03:30:03下载
- 积分:1
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FPGA verilog代码
说明: 数电实验FPGA verilog代码,包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)
- 2020-04-29 11:16:05下载
- 积分:1
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8b10b
ALERA fpga 8B10B转换源码,用于实现8B转10B,10B转8B功能。(ALTERA fpga 8B10B conversion source, used to achieve 8B to 10B, 10B to 8B function)
- 2020-09-13 02:07:59下载
- 积分:1
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5. For the key to enter a password lock, assuming that reset after the seven lam...
5对于进入密码锁的钥匙,假设复位后七节灯显示为" 0",而使用sw1、sw2两个,则sw2-> sw1-> sw1-> sw2,则表示解锁右侧将导致七节灯显示为" 8"
- 2023-06-12 23:35:07下载
- 积分:1
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EDA_C2262
Quartus_II_9.0破解器有明确的破解Quartus_II_9.0的步骤(Quartus_II_9. 0 cracked the clear cracked Quartus_II_9. 0 steps)
- 2011-11-07 21:31:47下载
- 积分:1
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fir_lms
基于FIR滤波器的LMS自适应算法的FPGA实现,verilog语言(FIR filter based on LMS adaptive algorithm on FPGA, VHDL language)
- 2015-10-11 19:23:03下载
- 积分:1