扰码器的verilog实现,参考802.11a相关标准

The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The 720-channel source driver has true 6-bit resolution, which (The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The )

至于FSK调制原理就不多说了，这里做的一个实验是二进制频移键控。发送一组码元，通过响应的键控电路监测是发1还是发0然后选择频率控制正余弦电路波形。-see

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

讲解快速傅里叶变换--FFT快速算法的文章。-On Fast Fourier Transform- FFT fast algorithm for the article.

本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn

这通过反馈来实现一个 17 位伪随机的无符号计数器异或的位 0 和 3。 注意 ︰ 如果也绝不是独家使用相反，这会反相平行的位模式 & 这将意味着所有位都零是一种有效模式和所有那些不都是有效。  目前所有的都是有效的。

例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)

matlab dsp building fpga(matlab dsp building )

关键词：清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码，内含中断，串口，以及31个指令的实现，读写内存，控制器，ALU，寄存器，分频等模块，小作业什么的可以直接从里面摘抄，为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)

des code source vhdl sur fpga