扰码器的verilog实现,参考802.11a相关标准

双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家-Bi-directional shift register of the VHDL source code, prepared by their own experiments can be used Thank you

LCD Interface_Xilinx.CPLD源码参考设计(LCD Interface Xilinx CPLD)

GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)

利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)

频率计，测量频率。可测范围为100HZ至60khz.测量比较稳定。基于MSPg2553(Frequency meter, measuring frequency. Measurable range 100HZ to 60khz. Stable measurement)

说明：  用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)

数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)

ahb to apb master verification

中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号 (IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)

实现大型LED屏显示的CPLD程序，对FPGA学习很有帮助-To achieve large-scale LED screen display of the CPLD program, very helpful for learning FPGA