这是led流水灯的vhdl描述，很好的啊

带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)

巴克码装到信息内同时将巴克码识别出来，实现帧同步的VHDL设计(Barker code loaded to the information identified while Barker code, VHDL design to achieve frame synchronization)

example of BCH and RS codecs

说明：  使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。(The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.)

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

VHDL语言，实现穿行数据接收的功能，将异步串口的数据转换为八位数据存储。

基于verilog的FIR滤波器程序设计（调试过的）-verilog

说明：  asssembly ccode to turn on 7 segmen

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.