单周期CPU

这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)

I2C verilong code  详细代码分析，根据协议每一步都有分析，进过验证，代码分slave和master部分，代码比较成熟

应用背景原创VERILOG HDL 实现数据指令CACHE的操作，LRU替换算法，包括1路组相连和2路组相连，包含ISE工程文件，亲测可用，初学者必备关键技术采用verilog语言设计的ARM cache，包含tb文件，写回策略。LRU替换算法

XAPP224 VHDL Data Recovery design file

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

讲述软解调很不错的一片文档，主要阐述的是8PSK的软解调FPGA实现，但对8PSK的软解调原理阐述很清楚，没有多余的东西，但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)

verilog实现计时器timer，可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.