UVM SV阶段

通过matlab对于声音进行处理，实现FFT，均值，方差，中值滤波，自相关分析，白噪声等处理(Matlab sound processing, FFT, mean, variance, median filtering, autocorrelation analysis, white noise and processing)

Quartus环境下多路选择器的编写代码，适合初学数字逻辑设计的进行学习(MUX in Quartus)

说明：  viterbi decode by verilog

此程序是Verilog HDL语言读写RAM的程序希望大家有用(This is Verilog HDL Promang)

使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)

实现了光OFDM模块的各个功能，同时仿真分析了OFDM的载波幅度谱、相位谱、每个载波对应的时域信号、整个时域/频域的OFDM、每个接收符号的分布图。计算了相位差等等(To achieve the various functions of the optical OFDM module, the simulation analysis of the the the OFDM carrier amplitude spectrum and phase spectrum, and the time domain signal corresponding to each carrier, the whole time domain/frequency domain OFDM, each reception symbol maps. Calculated phase difference)

it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scripts, pdfs, netlists etc. and a MIPS IP package

连乘,乘法可以用简单的for循环，我这里用的是移位寄存器来做，而且是用来两个移位寄存器(this is a tool that function is multiplay,it use a special way to do multiplay .it will teach you the how to use labview )

In computer storage, multipath I/O is a fault-tolerance and performance enhancement technique whereby there is more than one physical path between the CPU in a computer system and its mass storage devices through the buses, controllers, switches, and bridge devices connecting them

用FPGA实现数字锁相环，开发环境为ISE(Using FPGA digital phase-locked loop, development environment for ISE)