verilog 多周期CPU设计

xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)

说明：  s29gl256s nor flash 源代码(s29gl256s device source code)

图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)

你好，

单口RAM带CLR信号的verilog程序。很详细的.(Single-port RAM with a CLR signal)

简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)

单周期CPU，Verilog源码，                                              解压即可运行。

DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit(DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit)

嗨伙计， 附加的文件包含了完整的工作示例通用验证方法学基于系统VERILOG

说明：  内部含3个模块，使用DDS产生200k与500k的正弦波，两者相加后过数字低通滤波（通带0-200k，阻带400k以上），并将波形输出，实测FFT分析中看不到500k分量。其中数字滤波器采用MATLAB设计（FIR+等波纹，阻带衰减-80dB）(There are three modules in the system. DDS is used to generate 200K and 500K sine waves. After adding the two modules, the digital low-pass filter (passband 0-200k, stopband above 400k) is used, and the waveform is output. 500K component can not be seen in the actual FFT analysis. The digital filter is designed by MATLAB (FIR + equal ripple, stopband attenuation - 80dB))