NIOS II IDE 编程， 定时器测试程序，仅供参考。

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.

maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program

Quartus_II_9.0破解器有明确的破解Quartus_II_9.0的步骤(Quartus_II_9. 0 cracked the clear cracked Quartus_II_9. 0 steps)

本程序给出了在FPGA板上实现LCD显示的方法。支持的FPGA有APARTAN 3、SPARTAN 3E、VIRTEX 3等

32位扰码器的verilog代码，编译通过(The Verilog code of 32_bit scrambler)

用于ATmega128的一些通讯程序，包含I2C　UART，SPI等接口，用ICCAVR编译(for ATmega128 some communications procedures, including UART I2C, SPI interfaces with ICCAVR compiler)

说明：  对fpga的学习有一点帮助，属于较为基础的部分(It has a little help to the study of FPGA, which belongs to the more basic part)

数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。(The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.)