NIOS II IDE 编程， 定时器测试程序，仅供参考。

UVM 1.2 golden code, (code for UVM, )

本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)

This file contains async fifo design

基于nios的vga显示实验，自制的ip核。可以按照自己的需求改写ip(Nios to vga display ip nuclear experiments, homemade. Can be rewritten in accordance with their own needs ip)

表决器，简单实现了表决功能，无显示功能 -vote

能够成功的实现走马灯功能，使LED循环亮灭(To succeed the implementation of the version function, make the LED circular light out)

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench

一个FPGA的AVR_Core 仅供测试~-AVR_Core an FPGA-only test ~

一段很好地讲述PWM的VHDL硬件代码，可以在不同SOPC上运行实现