上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换...

乘法器功能 直接实现两个数字信号的相乘～-Multiplier features two digital signal direct implementation of the multiplication ~

parity encoder test bench

本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.

说明：  FPGA接收串口UART发来的指令设定温度报警值，实时采集DS18B20温度传感器并显示，带报警功能(FPGA receives the instruction from UART, sets the temperature alarm value, collects and displays DS18B20 temperature sensor in real time, with alarm function)

说明：  使用vivado和Xilinx开发板实现VGA图像显示，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize VGA image display, the development board is Xilinx artix-7)

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.

vhdl code for 8051 processor

8倍抽取的DDC模块。verilog写的，调试通过(failed to translate)

ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)

RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine