this come from alter ,you can look and find it on line about jtag.

自己编写的verilog语言 PWM实现的一种方法希望有用(verilog PWM)

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)

基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of

FPGA测序和DDS产生各种波形程序，用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)

电子时钟，可以显示四位，两位显示分钟，两位显示秒，可以用按键控制清零，以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)

基于VHDL的数字频率计的设计.pdf 基于VHDL的频率计设计 很好用的 希望要用的同志来下载 (基于VHDL的频率计设计 很好用的 希望要用的同志来下载 )

用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)

VHDL拔河电路的设计 基于cyclone V  VHDL拔河电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V

Diagram and how-to-make instructions pack of 6 diferent Amplifiers

Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)