this come from alter ,you can look and find it on line about jtag.

实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)

HDL example source code 2/5 dff_en

EDA技术与VHDL课件，利用EDA技术进行电子系统设计(EDA technology and VHDL courseware, the use of EDA technology for electronic system design)

基于diligent公司的basys2开发板的四位有符号二进制数的除法

数字ic设计，二级缓存，格雷码，深度256，(Digital IC design, two level cache, gray code, depth 256.)

说明：  misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

MX25L6445E开发时间，Verilog语言(MX25L6445E development time, Verilog language)

《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4

Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C

FPGA中按键弹跳消除模块的研究与应用，原理和例子都非常好-FPGA to eliminate bounce in key research and application modules, principles and examples are very good