this come from alter ,you can look and find it on line about jtag.

清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。(Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.)

vhdl code for 8051 processor

verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用(verilog code for serial port transmit and receive code, with source code and test files, and accurate available)

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件-Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document

xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material

vhdl code for decoder and detemines the basic mechanism of gates of decoder

costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块(costas the verilog program, including multipliers, DDS, phase detector, loop filter modules)

quick reference guide to verilog HDL

verilog 写的工程，是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)

vhdl code for multiplexer and detemines how multiplexer works