-
ISE7.1,采用VIRTEX
ISE7.1,采用VIRTEX-II芯片。实现adc数据采样,平均,通道选择,采样时钟选择,数据格式调整,内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
- 2022-03-28 19:34:46下载
- 积分:1
-
基于FPGA(VHDL)的LCD1602液晶显示程序
本工程中实现的是FPGA控制的LCD1602液晶显示屏的控制程序,实现了LCD1602液晶显示屏上显示一个四位十进制的频率,其中的频率产生模块在另一个程序中出现,没有在该模块中体现,但是仍能清楚到看到LCD1602的控制过程
- 2023-02-01 15:55:04下载
- 积分:1
-
Endat_2
Endat slave interface
- 2021-04-21 19:38:49下载
- 积分:1
-
rs_204_188----v1.0
RS 编码和解码Verilog Code, 实现了RS(204,188)的编码和译码;(RS Coding and Decoding Verilog code, implement RS(204,188) )
- 2021-03-25 20:29:14下载
- 积分:1
-
rs-codec(255-223)
RS编码是一种纠错码,本程序实现RS(255,223)用FPGA 实现RS编码,程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)
- 2021-05-13 00:30:02下载
- 积分:1
-
3P3_wimdow
图像插值算法,窗口为3*3,用于图像的除去死点,以及提高清晰度或者使图像柔和(3*3 window)
- 2012-02-28 15:36:02下载
- 积分:1
-
Get-20-point
this program get 20 point from user and draw functions.
- 2014-01-09 03:25:06下载
- 积分:1
-
table-for-sin-functionof-
DDS中的正余弦生成,初始相位相差90度,可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)
- 2013-12-17 22:09:56下载
- 积分:1
-
The VHDL source code digital clock, you can achieve at school, school grade feat...
数字钟的VHDL源程序,可以实现校时,校分等功能,并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
- 2023-02-06 10:05:04下载
- 积分:1
-
Lab2
Simple ALU
Objectives
1. Explore simple ALU structure.
2. Working with components
3. Working with language templates in ModelSim
4. Making a test bench and simulation using ModelSim
- 2017-01-13 19:28:54下载
- 积分:1