ps2接口源程序。标准的键盘和鼠标接口，在Xilinx SpartanII XC2S200 实验板上通过验证...

ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.

本工程中实现的是FPGA控制的LCD1602液晶显示屏的控制程序，实现了LCD1602液晶显示屏上显示一个四位十进制的频率，其中的频率产生模块在另一个程序中出现，没有在该模块中体现，但是仍能清楚到看到LCD1602的控制过程

Endat slave interface

RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code，　implement RS（204,188) )

RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)

图像插值算法，窗口为3*3,用于图像的除去死点，以及提高清晰度或者使图像柔和(3*3 window)

this program get 20 point from user and draw functions.

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim